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MCP2030
T CSH
T CSH
CS
2
6
7
9
T CSSC
4
16 Clocks for Read Command,
Address and Dummy Data
T SCCS T CS1
T CS0
T CSSC
8 16 Clocks for Read Result
10
T CSSC T CS 1
T CS0
T HI T LO
SCLK/ALERT
ALERT
(output)
SCLK
(input)
MSb
1/F SCLK
LSb
ALERT
(output)
SCLK
(input)
ALERT
(output)
1
T SU T HD
T DO
LFDATA/RSSI/
CCLK/SDIO
LFDATA
(output)
SDI
(input)
3
5
LFDATA
(output)
SDO
(output)
LFDATA
(output)
MCU SPI Read Details:
1.
2.
3.
4.
5.
6.
Drive the open collector ALERT output low.
? To ensure no false clocks occur when CS drops.
Drop CS
? SCLK/ALERT becomes SCLK input.
? LFDATA/CCLK/SDIO becomes SDI input.
Change LFDATA/CCLK/SDIO connected pin to output.
? Driving SPI data.
Clock in 16-bit SPI Read sequence.
? Command, address and dummy data.
Change LFDATA/CCLK/SDIO connected pin to input.
Raise CS to complete the SPI Read entry of command and address.
7.
8.
9.
10.
Drop CS.
? AFE SCLK/ALERT becomes SCLK input.
? LFDATA/CCLK/SDIO becomes SDO output.
Clock out 16-bit SPI Read result.
? First seven bits clocked-out are dummy bits.
? Next eight bits are the Configuration register data.
? T he last bit is the Configuration register row parity bit.
Raise CS to complete the SPI Read.
Change SCLK/ALERT back to input.
Note:
The T CSH is considered as one clock. Therefore, the
Configuration register data appears at 6th clock after T CSH .
FIGURE 5-11:
DS21981A-page 48
SPI Read Sequence.
? 2005 Microchip Technology Inc.
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